vhdl.js 2.5 KB

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  1. module.exports = function(hljs) {
  2. // Regular expression for VHDL numeric literals.
  3. // Decimal literal:
  4. var INTEGER_RE = '\\d(_|\\d)*';
  5. var EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;
  6. var DECIMAL_LITERAL_RE = INTEGER_RE + '(\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';
  7. // Based literal:
  8. var BASED_INTEGER_RE = '\\w+';
  9. var BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';
  10. var NUMBER_RE = '\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';
  11. return {
  12. case_insensitive: true,
  13. keywords: {
  14. keyword:
  15. 'abs access after alias all and architecture array assert assume assume_guarantee attribute ' +
  16. 'begin block body buffer bus case component configuration constant context cover disconnect ' +
  17. 'downto default else elsif end entity exit fairness file for force function generate ' +
  18. 'generic group guarded if impure in inertial inout is label library linkage literal ' +
  19. 'loop map mod nand new next nor not null of on open or others out package parameter port ' +
  20. 'postponed procedure process property protected pure range record register reject ' +
  21. 'release rem report restrict restrict_guarantee return rol ror select sequence ' +
  22. 'severity shared signal sla sll sra srl strong subtype then to transport type ' +
  23. 'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor',
  24. built_in:
  25. 'boolean bit character ' +
  26. 'integer time delay_length natural positive ' +
  27. 'string bit_vector file_open_kind file_open_status ' +
  28. 'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' +
  29. 'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' +
  30. 'real_vector time_vector',
  31. literal:
  32. 'false true note warning error failure ' + // severity_level
  33. 'line text side width' // textio
  34. },
  35. illegal: '{',
  36. contains: [
  37. hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.
  38. hljs.COMMENT('--', '$'),
  39. hljs.QUOTE_STRING_MODE,
  40. {
  41. className: 'number',
  42. begin: NUMBER_RE,
  43. relevance: 0
  44. },
  45. {
  46. className: 'string',
  47. begin: '\'(U|X|0|1|Z|W|L|H|-)\'',
  48. contains: [hljs.BACKSLASH_ESCAPE]
  49. },
  50. {
  51. className: 'symbol',
  52. begin: '\'[A-Za-z](_?[A-Za-z0-9])*',
  53. contains: [hljs.BACKSLASH_ESCAPE]
  54. }
  55. ]
  56. };
  57. };